Leading a team of Verification Engineers in development of UVM testbenches for high capacity enterprise class tape storage device control electronics.

OVM/UVM testbench development for focal plane image capture, telemetry, and storage devices;

OVM testbench development for SAS/SATA RAID controller electonics;

* VERA testbench development * Verification team lead

* ASIC Design and Verification Engineer * Performed functional verification of Fibre Channel protocol switching ASICs on a team of 6-10 design and verification engineers. * Developed Object-Oriented testbench and device emulation code in VERA hardware verification language. * Developed test strategies and planned specific device tests in VERA and System-C. * Developed specific tests for various sub blocks and IP blocks in Fibre Channel switch ASIC. * Interacted with suppliers of embedded high speed SERDES and XAUI cores from third-party suppliers to resolve IP design bugs and system integration issues. * Administered and analyzed test regression runs. * Migrated tests to FPGA-based emulation target hardware. * Debugged FPGA problems and develop simulation tests to reproduce them. * Developed performance analysis tests and hardware models.

* Led design/debug team developing telemetry hardware for seismic data acquisition systems. * Developed embedded microcode for bit-slice arithmetic units in seismic data acquistion and pre-processing systems. * Conducted lab debug of RTOS-based embedded firmware code. * Aided deployment of systems to field applications, and resolved field-discovered problems in customer-facing environments.

* ASIC Design and Verification Engineer * Hardware design/verification of host and device interface ASICS in tape-drive control systems. * Responsible for ASIC development from architecture through design, verification, synthesis and timing closure. * Wrote and reviewed architecture and design specifications for tape-drive host-adapter ASICs. * Architected and designed error-correcting memory buffer controller ASIC. * Worked with firmware team to integrate and debug ASIC components of tape drive control subsystems. * Analyzed hardware and software operational anomalies in RTOS kernel-based software environment using logic analyzers, in-circuit emulators, and oscilloscopes. * Wrote Verilog testbenches running on NC-Verilog to verify ASICs at the RTL and gate-level. * Used Synopsys PrimeTime for formal equivalency checking of RTL to gate-level. * Wrote embedded diagnostic firmware in C. * Wrote micro-sequencer code assembler in PERL.