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Smts Silicon Design EngineerAmd Jul 2022 - PresentSanta Clara, California, Us -
Vlsi Physical Design Engineer Iv, ExpertHewlett Packard Enterprise Jan 2018 - Jul 2022Houston, Texas, Us- Technical Lead - Digital place and route block construction and STA flows- 7nm and 16nm SerDes-based bridge and switch ASIC implementation from synthesis to Oasis- Synopsys DC, ICC2, and PrimeTime-SI expertise- SDC timing constraint development- Flow development within a Perl-based job management system- Extensive tool methodology development, primarily in Tcl- Physical verification with IC Validator- Formal verification with Conformal- Power integrity checking with RedHawk- Utilization of multiple clock network methodologies- Collaboration with VLSI groups across different organizations- Git and SOS revision control
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Senior Manufacturing Engineer - Space Systems GroupSierra Nevada Corporation Sep 2016 - Jan 2018Sparks, Nv, Us■ Plan, coordinate, support, and document production of high-reliability electronic assemblies for spacecraft■ Review, approve, and help develop engineering drawings for circuit card assemblies, PWBs, box-level assemblies■ Develop, approve revision-controlled assembly work instructions, procedures, and non-conformance dispositions■ Evaluate suppliers for conformance to product requirements, NASA, MIL, IPC and other industry quality standards
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Senior Member Of Technical StaffTezzaron Semiconductor Jul 2015 - Jun 2016Austin, Texas, Us■ Supported 28nm and 40nm high-speed SerDes bridge and IO protocol chip implementation■ Mentored junior engineers in IC physical implementation concepts, flows, and problem solving■ Physical design of 4.0 GHz, 2.0GHz and 1.0 GHz digital blocks using Cadence EDI/Encounter■ Implemented Static Timing Analysis flow for block and top level using Cadence Tempus■ Developed flow and created models for Power and Rail analysis with Cadence Voltus ■ Developed and documented electromigration analysis and mitigation methodology■ Refined timing and power signoff constraints, based on experience and foundry specs■ Provided feedback to improve top-level floorplan, power network, and signal integrity
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Staff Design Engineer, Physical Implementation, Zsp Product DivisionVerisilicon Jul 2006 - Jul 2015Shanghai, Shanghai, Cn■ ZSP Division was part of LSI Logic until July 2006■ RTL to GDS-II layout of ASIC/SoCs & hard macros featuring the ZSP digital signal processor■ Critical and lead roles on chips in 90, 65, 40, and 28nm CMOS processes■ Synthesis, Place, Clock-Tree Synthesis (CTS), Route, ECO, Parasitic Extraction■ Static Timing Analysis (STA), Signal Integrity (SI) and noise analysis■ Design multi-domain power networks with gating and isolation, using Unified Power Format (UPF)■ Direct and review test chip top-level physical design tasks performed by Shanghai team■ Analyze IR Drop and Electromigration (EM) maps and reports to verify power network design■ Characterize performance, power, and area (PPA) to drive improved Quality of Results (QoR)■ Tabulate PPA metrics into spreadsheets and slides for analysis, customer opportunities■ Implement Design-for-Test (DFT) and Design-for-Manufacturability (DFM) methodologies■ Engage with customer design teams, managers, and executives on critical projects ■ Design and verify processor sub-blocks using Verilog and SystemVerilog ■ Author technical documentation such as implementation guides and Statements of Work ■ Install, evaluate, and characterize third-party standard cell libraries and memory compilers ■ Develop test cases to demonstrate bugs in tools and methodology■ Chip package planning and I/O assignment
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Senior Design EngineerLsi Logic Aug 2000 - Jul 2006San Jose, Ca, Us■ RTL to GDS-II layout of ASIC/SoCs & hard macros featuring the ZSP digital signal processor■ Critical and lead roles on chips in 180 and 130nm CMOS processes■ Synthesis, Place, Clock-Tree Synthesis (CTS), Route, ECO, Parasitic Extraction■ Static Timing Analysis (STA), Signal Integrity (SI) and noise analysis■ Implement Design-for-Test (DFT) and Design-for-Manufacturability (DFM) methodologies■ Engage with customer design teams, managers, and executives on critical projects ■ Author technical documentation such as implementation guides■ Install, evaluate, and characterize third-party standard cell libraries and memory compilers ■ Develop test cases to demonstrate bugs in tools and methodology■ Chip package planning and I/O assignment
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Design Engineer IiLsi Logic Aug 1998 - Aug 2000San Jose, Ca, Us■ Critical tool and library support of internal ASIC design center customers in multiple locations■ Developed automation tools to migrate LSI design flow and libraries to Synopsys (Avanti) platform■ Developed physical layout and library automation tools in Perl, Tcl, and Scheme. ■ Filed and tracked software issues in Remedy database. ■ Coordinated tool bug/enhancement activity between end users and 3rd party tool developers■ Developed test cases to concisely illustrate tool bugs or enhancement requests
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Associate Manufacturing Engineer, Titan ProgramLockheed Martin Space Systems (Astronautics) Mar 1997 - Aug 1998Bethesda, Md, UsProvided production support, manufacturing process planning, and disposition instructions to rework defects for Titan II and Titan IV space launch vehicle electronic hardware components. Completed rockets successfully launched Lacrosse, Trumpet and Mentor intelligence (SIGINT) satellites, the NOAA-15 satellite, as well as the Cassini spacecraft to Saturn. Supported electronics production for Stardust, Space Shuttle (STS), and DoD satellites as needed. Worked closely with 6-8 unionized UAW assemblers to instruct, develop and refine procedures. Translated requirements from electronic design engineering team to assembly instructions and process plans. Developed process plans for production steps such as PCB wave solder, hand solder, surface mount solder, vapor degreasing, cleaning, masking, conformal coating, bonding, electronic component installation into chassis, wire harness construction, electrical, burn-in, and vibration testing.Contributed to solving process, material, and environmental challenges, such as the elimination of ozone-depleting chemicals in cleaning processes. Responsible for traceable documentation of assembly steps, ensuring conformance to military (MIL-spec) and design specifications. Presented finished hardware to U.S. Air Force personnel prior to closing and sealing process steps, and coordinated photographic documentation. Became certified as a Quality Planner, with authority to stamp manufacturing steps as complete and conforming to standards. Participated in lean initiative Kaizen events to improve quality and efficiency of processes.
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Electronics Production Support Engineer, Ocean Surveillance RadarTexas Instruments Defense Systems And Electronics Group (Dseg) Jun 1996 - Mar 1997Dallas, Tx, UsRedesigned digital and analog circuit card assemblies for ocean surveillance synthetic aperture radar systems used on Anti-Submarine Warfare (ASW) and Anti-Surface Warfare (ASuW) aircraft, such as the U.S. Navy P-3 Orion and S-3 Viking.Utilized Mentor Graphics and PSpice simulation for PCB layout and circuit design. Redesigned 400 Hz airborne power supply module to replace obsolete components and improve form factor.Designed test fixture for power supply module, and simulated functionality.Provided production floor engineering support, assisting with schematic interpretation and assembly techniques.Researched replacement circuit components and integrated circuits for obsolete parts, ensuring conformance to MIL specs.Planned and coordinated burn-in testing of PCB assemblies with updated components. Worked closely with mechanical engineers to integrate electronic assemblies into system chassis. Co-authored an assembly status-reporting script that operated on the TI information system. Transitioned PCB designs from plated through-hole (PTH) to surface-mount technology (SMT), learning about wave solder and surface mount machinery.Held a Secret-level national security clearance.
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Engineering Intern, Asic Tools And LibrariesSymbios Logic Jun 1995 - Aug 1995San Jose, Ca, UsEvaluated competitors' 0.5 micron standard cell and macro ASIC library and tool offerings. Contacted sales and engineering departments in order to research capabilities of competitors. Documented findings in reports and spreadsheets, and prepared presentation using PowerPoint. Delivered presentation before sales and engineering teams.
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Foundry Casting Pan Conveyor Worker, Grinder (Summer)General Motors Jun 1994 - Aug 1994Detroit, Michigan, UsOperated grinder to remove burrs and sharp edges from automotive part castings prior to the machining process step. Worked on pan conveyor line, using hand sledge hammer to remove sprue and runners from hot castings. Sorted castings into bins and activated automated bin retrieval and delivery system when bins were full. Operated shot peen machine to treat finished castings. Rotated to different foundry areas to become familiar with manufacturing process and equipment, and performed housekeeping duties, primarily sand cleanup, in various areas. Member of United Auto Workers (UAW) union during summer employment period.
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Foundry Core Room "Hot-Box" Operator (Summer)General Motors Jun 1993 - Aug 1993Detroit, Michigan, UsOperated "hot-box" machinery in a foundry to produce sand cores used in molds for casting of automotive parts, such as brake rotors and drums. Responsible for monitoring quality of cores, cleaning machine sand injection nozzles and mold surfaces to ensure smooth operation, and meeting daily production quota. Mixed and delivered sand to supply hoppers above machines. Observed safety procedures to avoid crushing and burn hazards. Member of United Auto Workers (UAW) union during summer employment period.
Scott Beeker Education Details
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University Of Illinois Urbana-ChampaignElectrical And Electronics Engineering
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University Of RochesterFundamentals Of Audio And Music Engineering
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Danville High SchoolDiploma
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Scott Beeker's role in his/her workplace is Vlsi Physical Design Engineer At Amd.
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What schools did Scott Beeker attend?
Scott Beeker attended University Of Illinois Urbana-Champaign, University Of Rochester, and Danville High School .
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