* – Lead technologist (90nm low-power Ultra Sparc microprocessor): interface between design teams and foundry. * – L2$ design on 130nm microprocessor. Lead on a successful porting with yield to alternate foundry. * – Developed an in-house PC graphical user interface tool for statistical analysis of tester data

* – Transferred ETOX Flash non-volatile memory (NVM) technology from AMD to Motorola * – Co-developed in research fab & qualified in manufacturing fab: 0.25/0.35umum 1T Embedded Flash for customer BOSCH * – Interface between NVM design and Device/Process team for optimal product design * – Designed SRAM memories for low power and high-speed products in mobile segment

Developing solutions and strategy for data insights and inferences in Si systems that connect from pre-design to in field system deployment. Addressing PPA, relatability and security challenges in Automotive/Datacenter/Mobile/Defense market segments

* Developed “Do Differently” engineering practices, fab guidelines and customer engagement processes leading to multiple products yielding first-time right on 28/14 nm nodes and in transitioning from a 2nd source to a 1st source foundry * Multiple customer product yield debugs on 28/22/14 nm nodes creating revenue/design wins * Co-developed 22nm FDSOI process technology and led the establishment of a novel IP/CAD ecosystem on FDSOI enabling a stand-alone competitive platform with differentiated offerings for customers in IOT, sensor and RF markets * Developed ML Computational Vision processor with tunable energy efficiency & throughput in 22-FDSOI * Technology lead on Corporate Strategy Team with charter of co-evaluating new investments/partnerships * Interface and support for C level executives on Technology and Product roadmap

* Responsible for all Memories Development in Global Foundries USA at various technology nodes including SRAM, EFuse and Emerging Memories across 28nm, 20nm and 14nm nodes. Role includes technology development, customer interface, design interface and test chips, yield and qualification in manufacturing fab, JDA.interface, development of test structure and functional arrays and development of simulation methodologies

Responsibilities include identifying new business opportunities based on existing core technology, developing new applications working closely with R&D: developed 3 new applications (layout optimization based on proximity effects/device optimization/design intent, layout optimization for reliability, and scanner setting optimization for a given mask based on design intent) resulting in business deals with major Japanese IDMs and major lithography equipment manufacturer.

* Developed Design for Manufacturability (DFM) strategy at ARM: cheaper in-house solutions, managed vendor relationships & tool evaluations in areas of lithography, layout-device interactions. JDA alliance lead on 45nm DFM. Developed automated test IP for design-device interactions for 32, 45 nm nodes. * ARM liaison for REALTY project: European Industrial/Academic consortium on Variability. * Developed memory circuit techniques that adapted to process and operational variability

* NOVEA: co-developed and qualified a novel single poly CMOS compatible NVM * E-fuse: developed an innovative and more reliable OTP memory for on-chip repair. * Responsibilities on above projects included: product development/characterization/qualification/reliability, external customer & foundry engagement, development of test lab infrastructure and leading engineering/debugging teams.. * Project Lead on device/technology/DFM/testing/design-interface for 65nm SRAM with Freescale/STM foundry alliance.

* Head and develop Direct to Foundry engagement. Responsibilities include: * Lead Technology evaluations, node migration, design sign off methodology, PPAC evaluations, cost modeling and FIP evaluation * Lead 2.5D/3D Chiplet program * Develop external research partnerships with research institutions and novel IP vendors * Staffing and growing the Si organization

Start-up/VC firms Adviser: pre-investment technical due diligence and post-investment problem solving in diverse domains of Biotechnology, Advanced CMOS, AI/ML, Battery Pack and Communication -- Expertise: Structured problem solving/Value creation/Mapping technology to Customer requirements/Strategy -- Recent consultancy examples: 2.5D/3D IC EDA Tools (Cadence), Strategy/Solution Creation (Autonomous Robots in Warehouse: IAMRobotics), Technical viability and strategy (Hybrid 5G-RF/FSO communication; 8Rivers Network), Fundamental Chemistry/Physics, data analysis & yield debug (Non-invasive Cancer Detection: Biological Dynamics), Market Application identification and penetration (High voltage/High power density Power supplies, Airity), Fab selection, process flow, manufacturing control & PDK development (Quantum computing: Psi Quantum), Power architecture/foundry interface (Blockchain: BCA), DFM and Litho-scanner applications/Strategy roadmap (EDA: Takumi), fundamental Physics/architecture/test/debug & staffing (Novel Memory: Adesto).

* Develop Strategy across portfolio of Memory Technologies and Products. * Establish processes and frameworks to improve X-functional engineering gaps. * Advisor to EVP on forward looking initiatives including partnerships/government contracts.